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INTEGRATED CIRCUITS
DATA SHEET
TDA8707 Triple RGB 6-bit video analog-to-digital interface
Product specification Supersedes dat of March 1995 File under Integrated Circuits, IC02 1996 Feb 01
Philips Semiconductors
Product specification
Triple RGB 6-bit video analog-to-digital interface
FEATURES * Triple analog-to-digital converter (ADC) * 6-bit resolution * Sampling rate up to 35 MHz * Power dissipation of 335 mW (typical) * Internal clamping function * TTL compatible digital inputs * -40 to +85 C operating temperature * CMOS digital outputs. APPLICATIONS * High-speed analog-to-digital conversion for video signals * VGA signal treatment. DESCRIPTION The TDA8707 is a CMOS triple 6-bit video low-power analog-to-digital converter (ADC) for RGB signals. QUICK REFERENCE DATA SYMBOL VDDA VDDD IDDA IDDD INL DNL EB fclk Ptot Notes PARAMETER analog supply voltage digital supply voltage analog supply current digital supply current integral non-linearity differential non-linearity effective bits maximum clock conversion rate total power dissipation fclk = 35 MHz; note 2 fclk = 35 MHz fclk = 35 MHz; ramp input; Tamb = 25 C fclk = 35 MHz; ramp input; Tamb = 25 C note 1 CONDITIONS MIN. 4.5 4.5 - - - - - 35 - TYP. 5.0 5.0 60 5 0.35 0.35 5.3 - 335
TDA8707
It converts the analog inputs into 6-bit binary coded digital words at a sampling rate of 35 MHz. All analog signal inputs are clamped. Analog-to-digital converter The TDA8707 implements 3 independent 6-bit analog-to-digital converters in CMOS process. These converters use a full-flash approach. Clamping feature An internal clamping circuit is provided in each of the 3 analog channels. The analog pins INR, ING and INB are switched, through series capacitors, to on-chip clamping levels during an active pulse on the clamp input CLP. Clamping level in the R, G and B channels is Code 0. Input buffers Internal buffers are provided to drive the analog-to-digital converter inputs. Their ratio can be adjusted externally at 1.5 or 2.0 with select input SLT.
MAX. 5.5 5.5 80 8 0.6 0.6 - - 485
UNIT V V mA mA LSB LSB bits MHz mW
1. The number of effective bits is measured with a clock frequency of 35 MHz. This value is given for a 4.43 MHz frequency on the R, G and B channels. 2. The external resistor (value 15 k) between VDDA and CLREF, fixing internal static currents, influences Ptot. ORDERING INFORMATION TYPE NUMBER TDA8707H 1996 Feb 01 PACKAGE NAME QFP44 DESCRIPTION VERSION plastic quad flat package; 44 leads; lead length 1.3 mm; body 10 x 10 x 1.75 mm SOT307-2 2
Philips Semiconductors
Product specification
Triple RGB 6-bit video analog-to-digital interface
BLOCK DIAGRAM
TDA8707
handbook, full pagewidth
CLREF 24
CLP 23
CLK 10
VDDA1 VSSA1
33 35
INR
34
BUFFER
CLAMPING CIRCUIT
6-BIT ADC
38, 40-44 R0 to R5 6
V DDA2 V SSA2
30 32 CLAMPING CIRCUIT 6-BIT ADC 6 3-8 G0 to G5
ING
31
BUFFER
V DDA3 V SSA3
27 29
TDA8707
CLAMPING CIRCUIT 6-BIT ADC 14-16, 18-20 B0 to B5 6 22 21 36 11 9
MGA919
INB
28
BUFFER
CREFH CREFL
26 25
VDDD2 VSSD2
SLT
V DDD1 VSSD1
Fig.1 Block diagram.
1996 Feb 01
3
Philips Semiconductors
Product specification
Triple RGB 6-bit video analog-to-digital interface
PINNING SYMBOL n.c. n.c. G0 G1 G2 G3 G4 G5 VSSD1 CLK VDDD1 n.c. n.c. B0 B1 B2 n.c. B3 B4 B5 VSSD2 VDDD2 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 DESCRIPTION not connected not connected GREEN data output; bit 0 (LSB) GREEN data output; bit 1 GREEN data output; bit 2 GREEN data output; bit 3 GREEN data output; bit 4 GREEN data output; bit 5 (MSB) digital supply ground 1 clock input digital supply voltage 1 not connected not connected BLUE data output; bit 0 (LSB) BLUE data output; bit 1 BLUE data output; bit 2 not connected BLUE data output; bit 3 BLUE data output; bit 4 BLUE data output; bit 5 (MSB) digital supply ground 2 digital supply voltage 2 SYMBOL CLP CLREF CREFL CREFH VDDA3 INB VSSA3 VDDA2 ING VSSA2 VDDA1 INR VSSA1 SLT n.c. R0 n.c. R1 R2 R3 R4 R5 PIN 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
TDA8707
DESCRIPTION clamping input ADCs current reference level input converter reference LOW level input converter reference HIGH level input analog supply voltage 3 BLUE analog input analog supply ground 3 analog supply voltage 2 GREEN analog input analog supply ground 2 analog supply voltage 1 RED analog input analog supply ground 1 select input buffer ratio not connected RED data output; bit 0 (LSB) not connected RED data output; bit 1 RED data output; bit 2 RED data output; bit 3 RED data output; bit 4 RED data output; bit 5 (MSB)
1996 Feb 01
4
Philips Semiconductors
Product specification
Triple RGB 6-bit video analog-to-digital interface
TDA8707
35 V SSA1
36 SLT
index corner n.c. n.c. G0 G1 G2 G3 G4 G5 V SSD1 1 2 3 4 5 6 7 8 9
34 INR
39 n.c.
37 n.c.
38 R0
44 R5
43 R4
42 R3
41 R2
40 R1
33 VDDA1 32 VSSA2 31 ING 30 V DDA2 29 VSSA3
TDA8707
28 INB 27 V DDA3 26 CREFH 25 CREFL 24 CLREF 23 CLP
CLK 10 VDDD1 11 B5 20 V SSD2 21 VDDD2 22
n.c. 12
n.c. 13
B0 14
B1 15
B2 16
n.c. 17
B3 18
B4 19
MGA920
Fig.2 Pin configuration.
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDA VDDD VDD VI Vi(p-p) Tstg Tamb Tj PARAMETER analog supply voltage (pins 27, 30 and 33) digital supply voltage (pins 11 and 22) supply voltage difference between VDDA and VDDD input voltage (pins 28, 31 and 34) AC input voltage for switching (pins 10 and 23; peak-to-peak value) storage temperature operating ambient temperature junction temperature referenced to VSSA referenced to VSSD CONDITIONS MIN. -0.3 -0.3 -0.5 - - -55 -40 - MAX. +6.5 +6.5 +0.5 VDDA VDDD +150 +85 +125 UNIT V V V V V C C C
THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 75 UNIT K/W
1996 Feb 01
5
Philips Semiconductors
Product specification
Triple RGB 6-bit video analog-to-digital interface
HANDLING
TDA8707
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. CHARACTERISTICS (see Tables 1 and 2) VDDA = VDDD = 4.5 to 5.5 V; VSSA and VSSD short-circuited together; VDDA - VDDD = -0.5 to +0.5 V; Tamb = -40 to +85 C; SLT = 0 V; CREFH = 2 V, CREFL = 0.5 V, CL = 15 pF; typical values measured at VDDA = VDDD = 5 V; VSSA = VSSD = 0 V and Tamb = 25 C; unless otherwise specified. SYMBOL Supply VDDA VDDD IDDA IDDD Inputs DIGITAL INPUTS (CLK: PIN 10 AND CLP: PIN 23) VIL VIH ILI CI ACL ICL CCL RCLREF VREFH VREFL REF ZCREF LOW level input voltage HIGH level input voltage input leakage current input capacitance 0 2.0 -10 - - -200 10 note 2 referenced to VSSA referenced to VSSA note 3 12 1.5 0.25 - - - - - 7 0.5 - 22 15 2.0 0.5 1.5 300 0.8 VDDD +10 - - +400 - - 2.5 0.75 - - V V A pF analog supply voltage digital supply voltage analog supply current digital supply current note 1 note 1 note 1 fclk = 35 MHz 4.5 4.5 - - 5.0 5.0 60 5 5.5 5.5 80 8 V V mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
CLAMP AND REFERENCES (CLREF: PIN 24, CREFL: PIN 25 AND CREFH: PIN 26) clamping accuracy input clamping current external series clamping capacitor external resistor on CLREF pin for current reference of converter converter reference voltage HIGH level applied to CREFH pin converter reference voltage LOW level applied to CREFL pin reference voltage difference between VREFH and VREFL internal ladder impedance between pins CREFH and CREFL LSB A nF k V V V
ANALOG INPUTS (INR: PIN 34, ING: PIN 31 AND INB: PIN 28) VI(p-p) full-range input voltage (peak-to-peak value) SLT = logic 0; gain = 1.5; note 4 SLT = logic 1; gain = 2.0; note 4 II CI input current input capacitance clamp off - - - - 1.0 0.75 5 7 - - 100 15 V V nA pF
1996 Feb 01
6
Philips Semiconductors
Product specification
Triple RGB 6-bit video analog-to-digital interface
SYMBOL INPUT ISOLATION ct VOL VOH crosstalk between INR, ING and INB - - - - PARAMETER CONDITIONS MIN. TYP.
TDA8707
MAX. -40
UNIT
dB
Outputs (R0 to R5: pins 38 and 40 to 44; G0 to G5: pins 3 to 8; B0 to B5: pins 14 to 16 and 18 to 20) LOW level output voltage HIGH level output voltage 0 4.0 0.5 VDDD V V
Switching characteristics CLOCK INPUT CLK (see Fig.3) fclk(max) tCPH tCPL maximum clock frequency clock pulse width HIGH clock pulse width LOW 35 10 12 - - - - - - MHz ns ns
Analog signal processing (50% clock duty cycle) fclk = 35 MHz LINEARITY INL DNL integral non-linearity differential non-linearity -3 dB analog bandwidth analog input settling time LOW-to-HIGH full scale square wave analog input settling time HIGH-to-LOW full scale square wave ramp input; Tamb = 25 C ramp input; Tamb = 25 C - - - - - - - fi = 4.43 MHz PAL modulated ramp - - - - 6 note 8 - 3 3 3 0.35 0.35 9 13 11 - -37 5.3 0.6 0.6 - 16 14 LSB LSB
BANDWIDTH (see Fig.5 and note 7) B tSTLH tSTHL f1 fall EB MHz ns ns
HARMONICS; note 6 fundamental harmonic harmonics, all components 0 - - - - - - 16 - - - dB dB
EFFECTIVE BITS effective bits bits
DIFFERENTIAL GAIN; note 5 Gdiff diff tdS th td tr tf tCLP differential gain 3 %
DIFFERENTIAL PHASE; note 5 differential phase PAL modulated ramp 2 deg
Timing (see Figs 3 and 4) sampling delay time output hold time output delay time clock rise time clock fall time active clamping duration 3 - - 5 5 4 ns ns ns ns ns s
1996 Feb 01
7
Philips Semiconductors
Product specification
Triple RGB 6-bit video analog-to-digital interface
Notes to the characteristics 1. VDDA and VDDD should be supplied from the same power supply and decoupled separately.
TDA8707
2. The analog supply current is directly proportional to the series resistance between VDDA and CLREF. 3. CREFH and CREFL are connected respectively to the top and bottom reference ladders of the 3 analog-to-digital converters. 4. VI(p-p) = (VREFL - VREFH)/buffer gain factor. See Table for gain factor selection. When clamping at code 0 is used, ( V REFH - V REFL ) active video signal amplitude VACT should be: V ACT = ---------------------------------------------buffer gain factor 5. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a digital-to-analog converter. 6. VI(p-p) = REF with fi = 4.43 MHz. 7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square-wave signal) in order to sample the signal and obtain correct output data. 8. Output data acquisition: output data is available after the maximum delay time of td. Table 1 Typical output coding (VREFH = 2 V; VREFL = 0.5 V referenced to VSSA, SLT = logic 0; buffer ratio = 1.5; Tamb = 25C) BINARY OUTPUT BITS STEP - 0 1 . 62 63 - VI(p-p) V REFL <0.333 = --------------1.5 0.349 0.364 . 1.317 1.333 V REFH >1.333 = ---------------1.5 D5 0 0 0 . 1 1 1 1 1 1 D4 0 0 0 D3 0 0 0 . 1 1 1 D2 0 0 0 . 1 1 1 D1 0 0 0 . 1 1 1 D0 0 0 1 . 0 1 1
Table 2
Mode selection SLT 0 BUFFER RATIO 1.5 TYPICAL VI(p-p) FULL SCALE V REFH - V REFL --------------------------------------1.5 V REFH - V REFL --------------------------------------2.0
1
2.0
1996 Feb 01
8
Philips Semiconductors
Product specification
Triple RGB 6-bit video analog-to-digital interface
TIMING DIAGRAMS
TDA8707
handbook, full pagewidth
t CPL t CPH CLK 1.4 V
sample N
sample N + 1
sample N + 2
IN R, G, B
t dS DATA D0 to D5 DATA N-2 DATA N-1 td DATA N
th 2.4 V DATA N+1
MLB759
1.4 V 0.4 V
Fig.3 Input timing.
handbook, full pagewidth
digital output level
63
black-level clamping 0 time CLP t CLP
MGA922
Fig.4 Clamp timing.
1996 Feb 01
9
Philips Semiconductors
Product specification
Triple RGB 6-bit video analog-to-digital interface
TDA8707
t STLH
handbook, full pagewidth
t STHL
code 64 VI code 0 2 ns 2 ns 50 % 50 %
CLK
50 %
50 %
MLD208
0.5 ns
0.5 ns
Fig.5 Analog input settling-time diagram.
1996 Feb 01
10
Philips Semiconductors
Product specification
Triple RGB 6-bit video analog-to-digital interface
INTERNAL CIRCUITRY
TDA8707
VDDD
V DDA
VSSD
VSSA VSSA
(a)
(b)
VDDD
VSSA
VSSA
VSSD
MGA925
(c)
(d)
(a) Digital inputs; pins 10, 23 and 36. (b) Analog inputs; pins 28, 31 and 34. (c) Current reference; pin 24. (d) Digital outputs; pins 3 to 8, 14 to 16, 18 to 20 and 40 to 44.
Fig.6 Internal circuitry.
1996 Feb 01
11
Philips Semiconductors
Product specification
Triple RGB 6-bit video analog-to-digital interface
APPLICATION INFORMATION
TDA8707
handbook, full pagewidth
R5
R4
R3
R2
R1
n.c.
R0
n.c.
SLT
RED 22 nF VSSA1 INR
100 nF VDDA1 VSSA2 22 nF GREEN 100 nF
44 n.c. 1
43
42
41
40
39
38
37
36
35
34 33
n.c.
2
32
G0
3
31
ING
G1
4
30
VDDA2 VSSA3 22 nF BLUE 100 nF
G2
5
29
G3
6
TDA8707
28
INB
G4
7
27
VDDA3
G5 VSSD1
8
26
CREFH
2V
2.2 nF
9 25 CREFL CLREF 10 24 5V 15 k 0.5 V
100 nF
CLK VDDD1
11 12 13 14 15 16 17 18 19 20 21 22
23
CLP
VSSD2 V DDD2 n.c. n.c. B0 B1 B2 n.c. B3 B4 B5 100 nF
MGA926
5V
Analog and digital supplies should be separated and decoupled. Supplies are not connected internally; also applicable to grounds. The internal reference currents are set by the series resistor between pin VDDA and CLREF. The resistor value should be in the range of 12 k and 15 k. It is recommended, if possible, to connect pins 1, 2, 12, 13, 17, 37 and 39 to VSSD.
Fig.7 Application diagram.
1996 Feb 01
12
Philips Semiconductors
Product specification
Triple RGB 6-bit video analog-to-digital interface
PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
TDA8707
SOT307-2
c
y X
A 33 34 23 22 ZE
e Q E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 A1 (A 3) Lp L
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 Q 0.85 0.75 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1996 Feb 01
13
Philips Semiconductors
Product specification
Triple RGB 6-bit video analog-to-digital interface
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
TDA8707
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Feb 01
14
Philips Semiconductors
Product specification
Triple RGB 6-bit video analog-to-digital interface
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8707
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Feb 01
15
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Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCDS47 (c) Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1100/03/pp16 Document order number: Date of release: 1996 Feb 01 9397 750 00605

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